Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-90
Prolog Sequences
Assembly/Compiler Coding Rule 57. (M impact, MH generality) In
routines that do not need a frame pointer and that do not have called routines
that modify
ESP, use ESP as the base register to free up EBP. This optimization
does not apply in the following cases: a routine is called that leaves ESP
modified upon return, for example, alloca; routines that rely on EBP for
structured or C++ style exception handling; routines that use
setjmp and
longjmp; routines that use EBP to align the local stack on an 8- or 16-byte
boundary; and routines that rely on EBP debugging.
If you are not using the 32-bit flat model, remember that EBP cannot be
used as a general purpose base register because it references the stack
segment.
Code Sequences that Operate on Memory Operands
Careful management of memory operands can improve performance.
Instructions of the form “
OP REG, MEM” can reduce register pressure by
taking advantage of scratch registers that are not available to the
compiler.
Assembly/Compiler Coding Rule 58. (M impact, ML generality) For
arithmetic or logical operations that have their source operand in memory and
the destination operand is in a register, attempt a strategy that initially loads
the memory operand to a register followed by a register to register ALU
operation. Next, attempt to remove redundant loads by identifying loads from
the same memory location. Finally, combine the remaining loads with their
corresponding ALU operations.
The recommended strategy follows:
1. Initially, operate on register operands and use explicit load and
store instructions, minimizing the number of memory accesses by
merging redundant loads.
2. In a subsequent pass, free up the registers that contain the operands
that were in memory for other uses by replacing any detected code
sequence of the form shown in Example 2-25 with
OP REG2, MEM1.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)