Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-66
Example 2-23 Algorithm to Avoid Changing the Rounding Mode
_fto132proc
lea ecx,[esp-8]
sub esp,16 ; allocate frame
and ecx,-8 ; align pointer on boundary of 8
fld st(0) ; duplicate FPU stack top
fistp qword ptr[ecx]
fild qword ptr[ecx]
mov edx,[ecx+4]; high dword of integer
mov eax,[ecx] ; low dword of integer
test eax,eax
je integer_QnaN_or_zero
arg_is_not_integer_QnaN:
fsubp st(1),st ; TOS=d-round(d),
; { st(1)=st(1)-st & pop ST}
test edx,edx ; what’s sign of integer
jns positive ; number is negative
fstp dword ptr[ecx]; result of subtraction
mov ecx,[ecx] ; dword of diff(single-
; precision)
add esp,16
xor ecx,80000000h
add ecx,7fffffffh ; if diff<0 then decrement
; integer
adc eax,0 ; inc eax (add CARRY flag)
ret
positive:
continued

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)