Intel ARCHITECTURE IA-32 User Manual

General Optimization Guidelines 2
2-67
Assembly/Compiler Coding Rule 32. (H impact, L generality) Minimize the
number of changes to the rounding mode. Do not use changes in the rounding
mode to implement the floor and ceiling functions if this involves a total of
more than two values of the set of rounding, precision and infinity bits.
Precision
If single precision is adequate, use it instead of double precision. This is
true because:
• Single precision operations allow the use of longer SIMD vectors,
since more single precision data elements can fit in a register.
• If the precision control (PC) field in the x87 FPU control word is set
to “Single Precision,” the floating-point divider can complete a
single-precision computation much faster than either a
double-precision computation or an extended double-precision
computation. If the PC field is set to “Double Precision,” this will
enable those x87 FPU operations on double-precision data to
complete faster than extended double-precision computation. These
characteristics affect computations including floating-point divide
and square root.
positive:
fstp dword ptr[ecx] ; 17-18 result of subtraction
mov ecx,[ecx] ; dword of diff(single precision)
add esp,16
add ecx,7fffffffh ; if diff<0 then decrement integer
sbb eax,0 ; dec eax (subtract CARRY flag)
ret
integer_QnaN_or_zero:
test edx,7fffffffh
jnz arg_is_not_integer_QnaN
add esp,16
ret
Example 2-23 Algorithm to Avoid Changing the Rounding Mode (continued)

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)