Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Processor Family Overview
1-11
The Front End
The front end of the Intel NetBurst microarchitecture consists of two
parts:
• fetch/decode unit
• execution trace cache
It performs the following functions:
• prefetches IA-32 instructions that are likely to be executed
• fetches required instructions that have not been prefetched
• decodes instructions into µops
• generates microcode for complex instructions and special-purpose
code
• delivers decoded instructions from the execution trace cache
• predicts branches using advanced algorithms
The front end is designed to address two problems that are sources of
delay:
• the time required to decode instructions fetched from the target
• wasted decode bandwidth due to branches or a branch target in the
middle of a cache line
Instructions are fetched and decoded by a translation engine. The
translation engine then builds decoded instructions into µop sequences
called traces. Next, traces are then stored in the execution trace cache.
The execution trace cache stores µops in the path of program execution
flow, where the results of branches in the code are integrated into the
same cache line. This increases the instruction flow from the cache and
makes better use of the overall cache storage space since the cache no
longer stores instructions that are branched over and never executed.
The trace cache can deliver up to 3 µops per clock to the core.

Intel ARCHITECTURE IA-32 Specifications

General

Brand	Intel
Model	ARCHITECTURE IA-32
Category	Processor
Language	English