Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-108
Tuning Suggestions
Tuning Suggestion 1. Rarely, a performance problem may be noted due
to executing data on a code page as instructions. The only condition
where this is likely to happen is following an indirect branch that is not
resident in the trace cache. If a performance problem is clearly due to this
problem, try moving the data elsewhere, or inserting an illegal opcode or
a
pause instruction immediately following the indirect branch. The latter
two alternative may degrade performance in some circumstances. 2-47
Tuning Suggestion 2. If a load is found to miss frequently, insert a
prefetch before it or, if issue bandwidth is a concern, move the load up to
execute earlier. 2-56

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)