Intel ARCHITECTURE IA-32 User Manual

Optimizing for SIMD Integer Applications 4
4-7
Signed Unpack
Signed numbers should be sign-extended when unpacking the values.
This is similar to the zero-extend shown above except that the
psrad
instruction (packed shift right arithmetic) is used to effectively sign
extend the values. Example 4-3 assumes the source is a packed-word
(16-bit) data type.
Example 4-2 Unsigned Unpack Instructions
; Input:
; MM0 source value
; MM7 0 a local variable can be used
; instead of the register MM7 if
; desired.
; Output:
; MM0 two zero-extended 32-bit
; doublewords from two low-end
; words
; MM1 two zero-extended 32-bit
; doublewords from two high-end
; words
movq MM1, MM0 ; copy source
punpcklwd MM0, MM7 ; unpack the 2 low-end words
; into two 32-bit doubleword
punpckhwd MM1, MM7 ; unpack the 2 high-end words
; into two 32-bit doublewords

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)