Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
B-48
Tags for front_end_event
Table B-3 provides a list of the tags that are used by various metrics
derived from the
front_end_event. The event names referenced in
column 2 can be found from the Pentium 4 processor performance
monitoring events.
Tags for execution_event
Table B-4 provides a list of the tags that are used by various metrics
derived from the
execution_event. These tags require programming
an upstream ESCR to select event mask with its
TagUop and TagValue
bit fields. The event mask for the downstream ESCR is specified in
column 4. The event names referenced in column 4 can be found in the
Pentium 4 processor performance monitoring events.
Table B-3 Table 3 Metrics That Utilize the Front-end Tagging Mechanism
Front-end MetricTags
1
1. There may be some undercounting of front end events when there is an overflow or underflow of the floating point
stack.
Additional MSR
See Event Mask Parameter for
Front_end_event
Memory_loads Set the TAGLOADS bit in
Uop_Type
NBOGUS
Memory_stores Set the TAGSTORES bit in
Uop_Type
NBOGUS

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)