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Intel ARCHITECTURE IA-32 User Manual

Intel ARCHITECTURE IA-32
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IA-32 Intel® Architecture Optimization
2-8
Avoid the use of conditionals.
Keep induction (loop) variable expressions simple.
Avoid using pointers, try to replace pointers with arrays and indices.
Coding Rules, Suggestions and Tuning Hints
This chapter includes rules, suggestions and hints. They are maintained
in separately-numbered lists and are targeted for engineers who are:
modifying the source to enhance performance (user/source rules)
writing assembly or compilers (assembly/compiler rules)
doing detailed performance tuning (tuning suggestions)
Coding recommendations are ranked in importance using two measures:
Local impact (referred to as “impact”) is the difference that a
recommendation makes to performance for a given instance, with
the impact’s priority marked as: H = high, M = medium, L = low.
Generality measures how frequently such instances occur across all
application domains, with the frequency marked as: H = high,
M = medium, L = low.
These rules are very approximate. They can vary depending on coding
style, application domain, and other factors. The purpose of including
high, medium and low priorities with each recommendation is to
provide some hints as to the degree of performance gain that one can
expect if a recommendation is implemented.
Because it is not possible to predict the frequency of occurrence of a
code instance in applications, priority hints cannot be directly correlated
to application-level performance gain. However, in important cases
where application-level performance gain has been observed, a more
quantitative characterization of application-level performance gain is
provided for information only (see: “Store-to-Load-Forwarding
Restriction on Size and Alignment” and “Instruction Selection” in this
document). In places where no priority is assigned, the impact has been
deemed inapplicable.

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Intel ARCHITECTURE IA-32 Specifications

General IconGeneral
Instruction Setx86
Instruction Set TypeCISC
Memory SegmentationSupported
Operating ModesReal mode, Protected mode, Virtual 8086 mode
Max Physical Address Size36 bits (with PAE)
Max Virtual Address Size32 bits
ArchitectureIA-32 (Intel Architecture 32-bit)
Addressable Memory4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers8 x 80-bit
MMX Registers8 x 64-bit
SSE Registers8 x 128-bit
RegistersGeneral-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point UnitYes (x87)

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