Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
3-32
Strip Mining
Strip mining, also known as loop sectioning, is a loop transformation
technique for enabling SIMD-encodings of loops, as well as providing a
means of improving memory performance. First introduced for
vectorizers, this technique consists of the generation of code when each
vector operation is done for a size less than or equal to the maximum
vector length on a given vector machine. By fragmenting a large loop
into smaller segments or strips, this technique transforms the loop
structure twofold:
• It increases the temporal and spatial locality in the data cache if the
data are reusable in different passes of an algorithm.
• It reduces the number of iterations of the loop by a factor of the
length of each “vector,” or number of operations being performed
per SIMD operation. In the case of Streaming SIMD Extensions,
this vector or strip-length is reduced by 4 times: four floating-point
data items per single Streaming SIMD Extensions single-precision
floating-point SIMD operation are processed. Consider
Example 3-18.
Example 3-18 Pseudo-code Before Strip Mining
typedef struct _VERTEX {
float x, y, z, nx, ny, nz, u, v;
} Vertex_rec;
main()
{
Vertex_rec v[Num];
....
for (i=0; i<Num; i++) {
Transform(v[i]);
}
continued

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)