Intel ARCHITECTURE IA-32 User Manual

Coding for SIMD Architectures 3
3-15
Assembly
Key loops can be coded directly in assembly language using an
assembler or by using inlined assembly (C-asm) in C/C++ code. The
Intel compiler or assembler recognize the new instructions and registers,
then directly generate the corresponding code. This model offers the
opportunity for attaining greatest performance, but this performance is
not portable across the different processor architectures.
Example 3-9 shows the Streaming SIMD Extensions inlined assembly
encoding.
Intrinsics
Intrinsics provide the access to the ISA functionality using C/C++ style
coding instead of assembly language. Intel has defined three sets of
intrinsic functions that are implemented in the Intel
®
C++ Compiler to
support the MMX technology, Streaming SIMD Extensions and
Streaming SIMD Extensions 2. Four new C data types, representing
64-bit and 128-bit objects are used as the operands of these intrinsic
functions.
__m64 is used for MMX integer SIMD, __m128 is used for
single-precision floating-point SIMD,
__m128i is used for Streaming
Example 3-9 Streaming SIMD Extensions Using Inlined Assembly Encoding
void add(float *a, float *b, float *c)
{
__asm {
mov eax, a
mov edx, b
mov ecx, c
movaps xmm0, XMMWORD PTR [eax]
addps xmm0, XMMWORD PTR [edx]
movaps XMMWORD PTR [ecx], xmm0
}
}

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)