Intel ARCHITECTURE IA-32 User Manual

Coding for SIMD Architectures 3
3-37
As one can see, all the redundant cache misses can be eliminated by
applying this loop blocking technique. If
MAX is huge, loop blocking can
also help reduce the penalty from DTLB (data translation look-aside
buffer) misses. In addition to improving the cache/memory
performance, this optimization technique also saves external bus
bandwidth.
Instruction Selection
The following section gives some guidelines for choosing instructions
to complete a task.
One barrier to SIMD computation can be the existence of
data-dependent branches. Conditional moves can be used to eliminate
data-dependent branches. Conditional moves can be emulated in SIMD
computation by using masked compares and logicals, as shown in
Example 3-21.
Example 3-21 Emulation of Conditional Moves
High-level code:
short A[MAX_ELEMENT], B[MAX_ELEMENT], C[MAX_ELEMENT],
D[MAX_ELEMENT], E[MAX_ELEMENT];
for (i=0; i<MAX_ELEMENT; i++) {
if (A[i] > B[i]) {
C[i] = D[i];
} else {
C[i] = E[i];
}
}
Assembly code:
xor eax, eax
continued

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)