Intel ARCHITECTURE IA-32 User Manual

7-1
7
Multi-Core and
Hyper-Threading Technology
This chapter describes software optimization techniques for
multithreaded applications running in an environment using either
multiprocessor (MP) systems or processors with hardware-based
multi-threading support. Multiprocessor systems are systems with two
or more sockets, each mated with a physical processor package. IA-32
processors that provide hardware multi-threading support include
dual-core processors and processor supporting Hyper-Threading
Technology
1
.
Computational throughput in a multi-threading environment can
increase as more hardware resources are added to take advantage of
thread-level or task-level parallelism. Hardware resources can be added
in the form of more than one physical-processor, and/or
processor-core-per-package, and/or logical-processor-per-core.
Therefore, there are some aspects of multi-threading optimization that
apply across MP, multi-core, and Hyper-Threading Technology. There
are also some specific microarchitectural resources that may be
implemented differently in different hardware multi-threading
configurations, e.g., execution resources are not shared across different
1. The presence of hardware multi-threading support in IA-32 processors can be detected by
checking the feature flag CPUID .1.EDX[28]. A return value of 1 in bit 28 indicates that at
least one form of hardware multi-threading is present in the physical processor package.
The number of logical processors present in each package can also be obtained from
CPUID. The application must check how many logical processors are enabled and made
available to application at runtime by making the appropriate operating system calls. See
the IA-32 Intel® Architecture Software Developer’s Manual, Volume 2A for more
information.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)