Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
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The other NOPs have no special hardware support. Their input and
output registers are interpreted by the hardware. Therefore, a code
generator should arrange to use the register containing the oldest value
as input, so that the NOP will dispatch and release RS resources at the
earliest possible opportunity.
Try to observe the following NOP generation priority:
• Select the smallest number of NOPs and pseudo-NOPs to provide
the desired padding.
• Select NOPs that are least likely to execute on slower execution unit
clusters.
• Select the register arguments of NOPs to reduce dependencies.
Summary of Rules and Suggestions
To summarize the rules and suggestions specified in this chapter, be
reminded that coding recommendations are ranked in importance
according to these two criteria:
• Local impact (referred to earlier as “impact”) – the difference that a
recommendation makes to performance for a given instance.
• Generality – how frequently such instances occur across all
application domains.
Again, understand that this ranking is intentionally very approximate,
and can vary depending on coding style, application domain, and other
factors. Throughout the chapter you observed references to these criteria
using the high, medium and low priorities for each recommendation. In
places where there was no priority assigned, the local impact or
generality has been determined not to be applicable.
The sections that follow summarize the sets of rules and tuning
suggestions referenced in the manual.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)