Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-20
Assembly/Compiler Coding Rule 3. (M impact, H generality) Arrange
code to be consistent with the static branch prediction algorithm: make the
fall-through code following a conditional branch be the likely target for a
branch with a forward target, and make the fall-through code following a
conditional branch be the unlikely target for a branch with a backward target.
Example 2-5 illustrates the static branch prediction algorithm. The body
of an
if-then conditional is predicted to be executed.
Example 2-5 Pentium 4 Processor Static Branch Prediction Algorithm
forw ard conditional branches not taken (fall through)
If <condition> {
...
}
Unconditional Branchestaken
JM P
for <condition> {
...
}
Backward Conditional Branchesaretaken
loop {
}<condition>

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)