Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
E-2
N
inst
is the number of instructions in the scope of one loop
iteration.
Consider the following example of a heuristic equation assuming that
parameters have the values as indicated:
where 60 corresponds to
Nlookup, 25 to Nxfer, and 1.5 to CPI.
The values of the parameters in the equation can be derived from the
documentation for memory components and chipsets as well as from
vendor datasheets.
Mathematical Model for PSD
The parameters used in the mathematics discussed are as follows:
psd prefetch scheduling distance (measured in number of
iterations)
il iteration latency
T
c
computation latency per iteration with prefetch caches
T
l
memory leadoff latency including cache miss latency,
chip set latency, bus arbitration, etc.
CAUTION. The values in this example are for
illustration only and do not represent the actual values
for these parameters. The example is provided as a
“starting point approximation” of calculating the
prefetch scheduling distance using the above formula.
Experimenting with the instruction around the
“starting point approximation” may be required to
achieve the best possible performance.
p
sd
60 25 N
pref
N
st
+()⋅+
1.5 N
inst
⋅
-----------------------------------------------------
=

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)