Intel ARCHITECTURE IA-32 User Manual

Optimizing Cache Usage 6
6-29
Minimize Number of Software Prefetches
Prefetch instructions are not completely free in terms of bus cycles,
machine cycles and resources, even though they require minimal clocks
and memory bandwidth.
Excessive prefetching may lead to performance penalties because issue
penalties in the front-end of the machine and/or resource contention in
the memory sub-system. This effect may be severe in cases where the
target loops are small and/or cases where the target loop is issue-bound.
One approach to solve the excessive prefetching issue is to unroll and/or
software-pipeline the loops to reduce the number of prefetches required.
Figure 6-4 presents a code example which implements prefetch and
unrolls the loop to remove the redundant prefetch instructions whose
prefetch addresses hit the previously issued prefetch instructions. In this
particular example, unrolling the original loop once saves six prefetch
instructions and nine instructions for conditional jumps in every other
iteration.
Figure 6-4 Prefetch and Loop Unrolling
OM15172
top_loop:
prefetchnta [edx+esi+32]
prefetchnta [edx*4+esi+32]
. . . . .
movaps xmm1, [edx+esi]
movaps xmm2, [edx*4+esi]
. . . . .
add esi, 16
cmp esi, ecx
jl top_loop
top_loop:
prefetchnta [edx+esi+128]
prefetchnta [edx*4+esi+128]
. . . . .
movaps xmm1, [edx+esi]
movaps xmm2, [edx*4+esi]
. . . . .
movaps xmm1, [edx+esi+16]
movaps xmm2, [edx*4+esi+16]
. . . . .
movaps xmm1, [edx+esi+96]
movaps xmm2, [edx*4+esi+96]
. . . . .
. . . . .
add esi, 128
cmp esi, ecx
jl top_loop
unrolled
iteration

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)