Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
6-30
Figure 6-5Figure demonstrates the effectiveness of software prefetches
in latency hiding. The X axis indicates the number of computation
clocks per loop (each iteration is independent). The Y axis indicates the
execution time measured in clocks per loop. The secondary Y axis
indicates the percentage of bus bandwidth utilization. The tests vary by
the following parameters:
1. The number of load/store streams. Each load and store stream
accesses one 128-byte cache line each, per iteration.
2. The amount of computation per loop. This is varied by increasing
the number of dependent arithmetic operations executed.
3. The number of the software prefetches per loop. (for example, one
every 16 bytes, 32 bytes, 64 bytes, 128 bytes).
As expected, the leftmost portion of each of the graphs in Figure 6-5
shows that when there is not enough computation to overlap the latency
of memory access, prefetch does not help and that the execution is
essentially memory-bound. The graphs also illustrate that redundant
prefetches do not increase performance.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)