Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Processor Family Overview
1-5
SSE and SSE2 instructions also introduced cacheability and memory
ordering instructions that can improve cache usage and application
performance.
For more on SSE, SSE2, SSE3 and MMX technologies, see:
IA-32 Intel® Architecture Software Developer’s Manual, Volume 1:
Chapter 9, “Programming with Intel® MMX™ Technology”;
Chapter 10, “Programming with Streaming SIMD Extensions
(SSE)”; Chapter 11, “Programming with Streaming SIMD
Extensions 2 (SSE3)”; Chapter 12, “Programming with Streaming
SIMD Extensions 3 (SSE3)”
Summary of SIMD Technologies
MMX™ Technology
MMX Technology introduced:
• 64-bit MMX registers
• support for SIMD operations on packed byte, word, and doubleword
integers
MMX instructions are useful for multimedia and communications
software.
Streaming SIMD Extensions
Streaming SIMD extensions introduced:
• 128-bit XMM registers
• 128-bit data type with four packed single-precision floating-point
operands
• data prefetch instructions
• non-temporal store instructions and other cacheability and memory
ordering instructions
• extra 64-bit SIMD integer support

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)