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Intel ARCHITECTURE IA-32 User Manual

Intel ARCHITECTURE IA-32
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IA-32 Intel® Architecture Optimization
9-16
thread enables the physical processor to operate at lower frequency
relative to a single-threaded version. This in turn enables the processor
to operate at a lower voltage, saving battery life.
Note that the OS views each logical processor or core in a physical
processor as a separate entity and computes CPU utilization
independently for each logical processor or core. On demand, the OS
will choose to run at the highest frequency available in a physical
package. As a result, a physical processor with two cores will often
work at a higher frequency than it needs to satisfy the target QOS.
For example if one thread requires 60% of single-threaded execution
cycles and the other thread requires 40% of the cycles, the OS power
management may direct the physical processor to run at 60% of its
maximum frequency.
However, it may be possible to divide work equally between threads so
that each of them require 50% of execution cycles. As a result, both
cores should be able to operate at 50% of the maximum frequency (as
opposed to 60%). This will allow the physical processor to work at a
lower voltage, saving power.
So, while planning and tuning your application, make threads as
symmetric as possible in order to operate at the lowest possible
frequency-voltage point.
Thread Migration Considerations
Interaction of OS scheduling and multi-core unaware power
management policy may create some situations of performance anomaly
for multi-threaded applications. The problem can arise for
multi-threading application that allow threads to migrate freely.
When one full-speed thread is migrated from one core to another core
that has idled for a period of time, an OS without a multi-core-aware
P-state coordination policy may mistakenly decide that each core

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Intel ARCHITECTURE IA-32 Specifications

General IconGeneral
Instruction Setx86
Instruction Set TypeCISC
Memory SegmentationSupported
Operating ModesReal mode, Protected mode, Virtual 8086 mode
Max Physical Address Size36 bits (with PAE)
Max Virtual Address Size32 bits
ArchitectureIA-32 (Intel Architecture 32-bit)
Addressable Memory4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers8 x 80-bit
MMX Registers8 x 64-bit
SSE Registers8 x 128-bit
RegistersGeneral-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point UnitYes (x87)

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