Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-74
Complex Instructions
Assembly/Compiler Coding Rule 40. (ML impact, M generality) Avoid
using complex instructions (for example, enter, leave, or loop) that have
more than four µops and require multiple cycles to decode. Use sequences of
simple instructions instead.
Complex instructions may save architectural registers, but incur a
penalty of 4 µops to set up parameters for the microcode ROM.
Use of the lea Instruction
In many cases, the lea instruction or a sequence of lea, add, sub and
shift instructions can replace constant multiply instructions. The lea
instruction can also be used as a multiple operand addition instruction,
for example:
lea ecx, [eax + ebx + 4 + a]
Using lea in this way may avoid register usage by not tying up registers
for operands of arithmetic instructions. This use may also save code
space.
If the
lea instruction uses a shift by a constant amount then the latency
of the sequence of µops is shorter if
adds are used instead of a shift, and
the
lea instruction may be replaced with an appropriate sequence of
µops. This, however, this increases the total number of µops, leading to
a trade-off.
Assembly/Compiler Coding Rule 41. (ML impact, M generality) If a lea
instruction using the scaled index is on the critical path, a sequence with
adds
may be better. If code density and bandwidth out of the trace cache are the
critical factor, then use the
lea instruction.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)