Intel ARCHITECTURE IA-32 User Manual

Using Performance Monitoring Events B
B-49
Table B-4 Metrics That Utilize the Execution Tagging Mechanism
Execution Metric Tags Upstream ESCR
Tag Value in
Upstream
ESCR
See Event Mask
Parameter for
Execution_
event
Packed_SP_retired Set the ALL bit in the
event mask and the
TagUop bit in the ESCR
of packed_SP_uop.
1 NBOGUS0
Scalar_SP_retired Set the ALL bit in the
event mask and the
TagUop bit in the ESCR
of scalar_SP_uop.
1 NBOGUS0
Scalar_DP_retired Set the ALL bit in the
event mask and the
TagUop bit in the ESCR
of scalar_DP_uop.
1 NBOGUS0
128_bit_MMX_retired Set the ALL bit in the
event mask and the
TagUop bit in the ESCR
of 128_bit_MMX_uop.
1 NBOGUS0
64_bit_MMX_retired Set the ALL bit in the
event mask and the
TagUop bit in the ESCR
of 64_bit_MMX_uop.
1 NBOGUS0
X87_FP_retired Set the ALL bit in the
event mask and the
TagUop bit in the ESCR
of x87_FP_uop.
1 NBOGUS0

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)