Intel ARCHITECTURE IA-32 User Manual

General Optimization Guidelines 2
2-21
Examples 2-6, Example 2-7 provide basic rules for a static prediction
algorithm.
In Example 2-6, the backward branch (
JC Begin) is not in the BTB the
first time through, therefore, the BTB does not issue a prediction. The
static predictor, however, will predict the branch to be taken, so a
misprediction will not occur.
The first branch instruction (
JC Begin) in Example 2-7 segment is a
conditional forward branch. It is not in the BTB the first time through,
but the static predictor will predict the branch to fall through
.
The static prediction algorithm correctly predicts that the Call
Convert
instruction will be taken, even before the branch has any
branch history in the BTB.
Example 2-6 Static Taken Prediction Example
Begin: mov eax, mem32
and eax, ebx
imul eax, edx
shld eax, 7
jc Begin
Example 2-7 Static Not-Taken Prediction Example
mov eax, mem32
and eax, ebx
imul eax, edx
shld eax, 7
jc Begin
mov eax, 0
Begin: call Convert

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)