Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-4
Use Available Performance Tools
• Current-generation compiler, such as the Intel C++ Compiler:
— Set this compiler to produce code for the target processor
implementation
— Use the compiler switches for optimization and/or
profile-guided optimization. These features are summarized in
the “Intel® C++ Compiler” section. For more detail, see the
Intel® C++ Compiler User’s Guide.
• Current-generation performance monitoring tools, such as VTune™
Performance Analyzer:
— Identify performance issues, use event-based sampling, code
coach and other analysis resource.
— Measure workload characteristics such as instruction
throughput, data traffic locality, memory traffic characteristics,
etc.
— Characterize the performance gain.
Optimize Performance Across Processor Generations
• Use a cpuid dispatch strategy to deliver optimum performance for
all processor generations.
• Use deterministic cache parameter leaf of cpuid to deliver scalable
performance that are transparent across processor families with
different cache sizes.
• Use compatible code strategy to deliver optimum performance for
the current generation of IA-32 processor family and future IA-32
processors.
• Use a low-overhead threading strategy so that a multi-threaded
application delivers optimal multi-processor scaling performance
when executing on processors that have hardware multi-threading
support, or deliver nearly identical single-processor scaling when
executing on a processor without hardware multi-threading support.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)