Intel ARCHITECTURE IA-32 User Manual

Stack Alignment D
D-5
Example D-1 Aligned esp-Based Stack Frames
void _cdecl foo (int k)
{
int j;
foo: // See Note A
push ebx
mov ebx, esp
sub esp, 0x00000008
and esp, 0xfffffff0
add esp, 0x00000008
jmp common
foo.aligned:
push ebx
mov ebx, esp
common: // See Note B
push edx
sub esp, 20
j = k;
mov edx, [ebx + 8]
mov [esp + 16], edx
foo(5);
mov [esp], 5
call foo.aligned
return j;
mov eax, [esp + 16]
add esp, 20
pop edx
mov esp, ebx
pop ebx
ret

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)