Intel ARCHITECTURE IA-32 User Manual

Introduction
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The manual consists of the following parts:
Introduction. Defines the purpose and outlines the contents of this
manual.
Chapter 1: IA-32 Intel
®
Architecture Processor Family Overview.
Describes the features relevant to software optimization of the current
generation of IA-32 Intel architecture processors, including the
architectural extensions to the IA-32 architecture and an overview of the
Intel NetBurst microarchitecture, Pentium M processor
microarchitecture and Hyper-Threading Technology.
Chapter 2: General Optimization Guidelines. Describes general code
development and optimization techniques that apply to all applications
designed to take advantage of the common features of the Intel NetBurst
microarchitecture and Pentium M processor microarchitecture.
Chapter 3: Coding for SIMD Architectures. Describes techniques
and concepts for using the SIMD integer and SIMD floating-point
instructions provided by the MMX™ technology, Streaming SIMD
Extensions, Streaming SIMD Extensions 2, and Streaming SIMD
Extensions 3.
Chapter 4: Optimizing for SIMD Integer Applications. Provides
optimization suggestions and common building blocks for applications
that use the 64-bit and 128-bit SIMD integer instructions.
Chapter 5: Optimizing for SIMD Floating-point Applications.
Provides optimization suggestions and common building blocks for
applications that use the single-precision and double-precision SIMD
floating-point instructions.
Chapter 6: Optimizing Cache Usage. Describes how to use the
prefetch instruction, cache control management instructions to
optimize cache usage, and the deterministic cache parameters.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)