Intel ARCHITECTURE IA-32 User Manual

E-1
E
Mathematics of Prefetch
Scheduling Distance
This appendix discusses how far away to insert prefetch instructions. It
presents a mathematical model allowing you to deduce a simplified
equation which you can use for determining the prefetch scheduling
distance (PSD) for your application.
For your convenience, the first section presents this simplified equation;
the second section provides the background for this equation: the
mathematical model of the calculation.
Simplified Equation
A simplified equation to compute PSD is as follows:
where
psd is prefetch scheduling distance.
Nlookup is the number of clocks for lookup latency. This
parameter is system-dependent. The type of memory
used and the chipset implementation affect its value.
Nxfer is the number of clocks to transfer a cache-line. This
parameter is implementation-dependent.
N
pref
and N
st
are the numbers of cache lines to be prefetched and
stored.
CPI is the number of clocks per instruction. This parameter
is implementation-dependent.
p
sd
Nlookup Nxfer N
pref
N
st
+()⋅+
CPI N
inst
⋅
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Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)