Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
6-48
Using the 8-byte Streaming Stores and Software Prefetch
Example 6-11 presents the copy algorithm that uses second level cache.
The algorithm performs the following steps:
1. Uses blocking technique to transfer 8-byte data from memory into
second-level cache using the
_mm_prefetch intrinsic, 128 bytes at
a time to fill a block. The size of a block should be less than one
half of the size of the second-level cache, but large enough to
amortize the cost of the loop.
2. Loads the data into an
xmm register using the _mm_load_ps intrinsic.
3. Transfers the 8-byte data to a different memory location via the
_mm_stream intrinsics, bypassing the cache. For this operation, it is
important to ensure that the page table entry prefetched for the
memory is preloaded in the TLB.
Example 6-11 A Memory Copy Routine Using Software Prefetch
#define PAGESIZE 4096;
#define NUMPERPAGE 512 // # of elements to fit a page
double a[N], b[N], temp;
for (kk=0; kk<N; kk+=NUMPERPAGE) {
temp = a[kk+NUMPERPAGE]; // TLB priming
// use block size = page size,
// prefetch entire block, one cache line per loop
for (j=kk+16; j<kk+NUMPERPAGE; j+=16) {
_mm_prefetch((char*)&a[j], _MM_HINT_NTA);
}
continued

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)