Intel ARCHITECTURE IA-32 User Manual

General Optimization Guidelines 2
2-65
If there is more than one change to rounding, precision and infinity bits
and the rounding mode is not important to the result; use the algorithm
in Example 2-23 to avoid synchronization issues, the overhead of the
fldcw instruction and having to change the rounding mode. The
provided example suffers from a store-forwarding problem which will
lead to a performance penalty. However, its performance is still better
than changing the rounding, precision and infinity bits among more than
two values.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)