Intel ARCHITECTURE IA-32 - Page 507

Using Performance Monitoring Events B
B-53
Memory Metrics Split Load Replays
1
Split Store Replays
1
MOB Load Replays
1
64k Aliasing Conflicts
1st-Level Cache Load Misses Retired
2nd-Level Cache Load Misses Retired
DTLB Load Misses Retired
Split Loads Retired
1
Split Stores Retired
1
MOB Load Replays Retired
Loads Retired
Stores Retired
DTLB Store Misses Retired
DTLB Load and Store Misses Retired
2nd-Level Cache Read Misses
2nd-Level Cache Read References
3rd-Level Cache Read Misses
3rd-Level Cache Read References
2nd-Level Cache Reads Hit Shared
2nd-Level Cache Reads Hit Modified
2nd-Level Cache Reads Hit Exclusive
3rd-Level Cache Reads Hit Shared
3rd-Level Cache Reads Hit Modified
3rd-Level Cache Reads Hit Exclusive
continued
Table B-6 Metrics That Support Qualification by Logical Processor and
Parallel Counting (continued)