Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
C-16
Table C-7 IA-32 x87 Floating-point Instructions
Instruction Latency
1
Throughput
Execution
Unit
2
CPUID 0F3n 0F2n 0x69n 0F3n 0F2n 0x69n 0F2n
FABS 3 2 1 1 FP_MISC
FADD 6 5 1 1 FP_ADD
FSUB 6 5 1 1 FP_ADD
FMUL 8 7 2 2 FP_MUL
FCOM 3 2 1 1 FP_MISC
FCHS 3 2 1 1 FP_MISC
FDIV Single Precision 30 23 30 23 FP_DIV
FDIV Double Precision 40 38 40 38 FP_DIV
FDIV Extended
Precision
44 43 44 43 FP_DIV
FSQRT SP 30 23 30 23 FP_DIV
FSQRT DP 40 38 40 38 FP_DIV
FSQRT EP 44 43 44 43 FP_DIV
F2XM1
4
100-
200
90-
150
60
FCOS
4
180-
280
190-
240
130
FPATAN
4
220-
300
150-
300
140
FPTAN
4
240-
300
225-
250
170
FSIN
4
160-
200
160-
180
130
FSINCOS
4
170-
250
160-
220
140
FYL2X
4
100-
250
140-
190
85
FYL2XP1
4
140-
190
85
continued

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)