Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
1-40
Pentium Processor Extreme Edition provide four logical processors in a
physical package that has two execution cores. Each core provides two
logical processors sharing an execution core and a cache hierarchy.
The Intel Core Duo processor provides two logical processors in a
physical package. Each logical processor has a separate execution core
(including first-level cache) and a smart second-level cache. The
second-level cache is shared between two logical processors and
optimized to reduce bus traffic when the same copy of cached data is
used by two logical processors. The full capacity of the second-level
cache can be used by one logical processor if the other logical processor
is inactive.
The functional blocks of these processors are shown in Figure 1-7.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)