Intel ARCHITECTURE IA-32 User Manual

Mathematics of Prefetch Scheduling Distance E
E-5
T
l
varies dynamically and is also system hardware-dependent. The static
variants include the core-to-front-side-bus ratio, memory manufacturer
and memory controller (chipset). The dynamic variants include the
memory page open/miss occasions, memory accesses sequence,
different memory types, and so on.
To determine the proper prefetch scheduling distance, follow these steps
and formulae:
• Optimize T
c
as much as possible
• Use the following set of formulae to calculate the proper prefetch
scheduling distance:
• Schedule the prefetch instructions according to the computed
prefetch scheduling distance.
• For optimized memory performance, apply techniques described in
“Memory Optimization Using Prefetch” in Chapter 6.
The following sections explain and illustrate the architectural
considerations involved in the prefetch scheduling distance formulae
above.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)