Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
D-2
alignment for __m64 and double type data by enforcing that these
64-bit data items are at least eight-byte aligned (they will now be
16-byte aligned).
For variables allocated in the stack frame, the compiler cannot
guarantee the base of the variable is aligned unless it also ensures that
the stack frame itself is 16-byte aligned. Previous IA-32 software
conventions, as implemented in most compilers, only ensure that
individual stack frames are 4-byte aligned. Therefore, a function called
from a Microsoft-compiled function, for example, can only assume that
the frame pointer it used is 4-byte aligned.
Earlier versions of the Intel C++ Compiler for Win32 Systems have
attempted to provide 8-byte aligned stack frames by dynamically
adjusting the stack frame pointer in the prologue of
main and preserving
8-byte alignment of the functions it compiles. This technique is limited
in its applicability for the following reasons:
• The main function must be compiled by the Intel C++ Compiler.
• There may be no functions in the call tree compiled by some other
compiler (as might be the case for routines registered as callbacks).
• Support is not provided for proper alignment of parameters.
The solution to this problem is to have the function’s entry point assume
only 4-byte alignment. If the function has a need for 8-byte or 16-byte
alignment, then code can be inserted to dynamically align the stack
appropriately, resulting in one of the stack frames shown in Figure D-1.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)