Intel ARCHITECTURE IA-32 User Manual

Mathematics of Prefetch Scheduling Distance E
E-9
For this particular example the prefetch scheduling distance is greater
than 1. Data being prefetched for iteration i will be consumed in
iteration i+2.
Figure E-4 represents the case when the leadoff latency plus data
transfer latency is greater than the compute latency, which is greater
than the data transfer latency. The following relationship can be used to
compute the prefetch scheduling distance.
In consequence, the iteration latency is also equal to the computation
latency, that is, compute bound program.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)