Intel ARCHITECTURE IA-32 User Manual

Using Performance Monitoring Events B
B-19
Speculative
Uops Retired
Number of uops
retired (include both
instructions executed
to completion and
speculatively
executed in the path
of branch
mispredictions).
uops_retired NBOGUS|BOGUS
Branching Metrics
Branches
Retired
All branch
instructions executed
to completion
Branch_retired MMTM|MMNM|MMTP|
MMNP
Tagged
Mispredicted
Branches
Retired
The events counts
the number of retired
branch instructions
that were
mispredicted. This
stat can be used with
precise event-based
sampling.
Replay_event; set
the following
replay tag:
Tagged_mispred_
branch
NBOGUS
Mispredicted
Branches
Retired
Mispredicted branch
instructions executed
to completion. This
stat is often used in a
per-instruction ratio.
Mispred_branch_
retired
NBOGUS
Misprediction
Ratio
Misprediction rate
per branch
(Mispredicted Branches
Retired) /(Branches
Retired)
All returns The number of return
branches
retired_branch_type RETURN
All indirect
branches
All returns and
indirect calls and
indirect jumps
retired_branch_type INDIRECT
All calls All direct and indirect
calls
retired_branch_type CALL
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression
Event Mask Value
Required

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)