Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
B-20
Mispredicted
returns
The number of
mispredicted returns
including all causes.
retired_mispred_
branch_type
RETURN
All conditionals The number of
branches that are
conditional jumps
(may overcount if the
branch is from build
mode or there is a
machine clear near
the branch)
retired_branch_type CONDITIONAL
Mispredicted
indirect
branches
All Mispredicted
returns and indirect
calls and indirect
jumps
retired_mispred_
branch_type
INDIRECT
Mispredicted
calls
All Mispredicted
indirect calls
retired_branch_type CALL
Mispredicted
conditionals
The number of
mispredicted
branches that are
conditional jumps
retired_mispred_
branch_type
CONDITIONAL
Trace Cache (TC) and Front-End Metrics
Page Walk Miss
ITLB
The number of page
walk requests due to
ITLB misses.
page_walk_type ITMISS
ITLB Misses The number of ITLB
lookups that resulted
in a miss. Page Walk
Miss ITLB.is less
speculative than
ITLB Misses and is
the recommended
alternative.
ITLB_reference MISS
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression
Event Mask Value
Required

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)