Intel ARCHITECTURE IA-32 User Manual

Using Performance Monitoring Events B
B-21
TC Flushes Number of TC
flushes (The counter
will count twice for
each occurrence.
Divide the count by 2
to get the number of
flushes.)
TC_misc FLUSH
Logical
Processor 0
Deliver Mode
The number of
cycles that the trace
and delivery engine
(TDE) is delivering
traces associated
with logical
processor 0,
regardless of the
operating modes of
the TDE for traces
associated with
logical processor 1. If
a physical processor
supports only one
logical processor, all
traces are
associated with
logical processor 0.
This is the formerly
known as “Trace
Cache Deliver Mode“
TC_deliver_mode SS|SB|SI
continued
Table B-1 Pentium 4 Processor Performance Metrics (continued)
Metric Description
Event Name or Metric
Expression
Event Mask Value
Required

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)