Intel ARCHITECTURE IA-32 User Manual

Using Performance Monitoring Events B
B-17
an expression built up from other metrics; for example, IPC is
derived from two single-event metrics.
• Column 2 provides a description of the metric in column 1. Please
refer to the previous section, “Pentium 4 Processor-Specific
Terminology” for various terms that are specific to the Pentium 4
processor’s performance monitoring capabilities.
• Column 3 specifies the performance monitoring event(s) or an
algebraic expression(s) that form(s) the metric. There are several
metrics that require yet another sub-event in addition to the counting
event. The additional sub-event information is included in column 3
as various tags, which are described in “Performance Metrics and
Tagging Mechanisms”. For event names that appear in this column,
refer to the IA-32 Intel® Architecture Software Developer’s Manual,
Volumes 3A & 3B.
• Column 4 specifies the event mask bit that is needed to use the
counting event. The addresses of various model-specific registers
(MSR), the event mask bits in Event Select Control registers
(ESCR), the bit fields in Counter Configuration Control registers
(CCCR) are described in IA-32 Intel® Architecture Software
Developer’s Manual, Volumes 3A & 3B.
The metrics listed in Table B-1 are grouped into several categories:
General Operation not specific to any
sub-system of the microarchitecture
Branching Branching activities
Trace Cache and Front End Front end activities and trace cache
operation modes
Memory Memory operation related to the
cache hierarch
Bus Activities related to Front-Side Bus
(FSB)
Characterization Operations specific to the processor
core

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)