Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
2-84
improve address alignment, a small piece of prolog code using
movsb/stosb with count less than 4 can be used to peel off the
non-aligned data moves before starting to use movsd/stosd.
• For cases where N is less than half the size of last level cache,
throughput consideration may favor either: (a) an approach using
REP string with the largest data granularity because REP string has
little overhead for loop iteration, and the branch misprediction
overhead in the prolog/epilogue code to handle address alignment is
amortized over many iterations (b) an iterative approach using the
instruction with largest data granularity; where the overhead for
SIMD feature detection, iteration overhead, prolog/epilogue for
alignment control can be minimized. The trade-off between these
approaches may depend on the microarchitecture.
An example of memset() implemented using stosd for arbitrary
counter value with the destination address aligned to doubleword
boundary in 32-bit mode is shown in Table 2-5.
• For cases N > half the size of last level cache, using 16-byte
granularity streaming stores with prolog/epilog for address
alignment will likely be more efficient, if the destination addresses
will not be referenced immediately afterwards.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)