Intel ARCHITECTURE IA-32 User Manual

General Optimization Guidelines 2
2-105
Assembly/Compiler Coding Rule 42. (M impact, H generality) inc
and
dec instructions should be replaced with an add or sub instruction,
because add and sub overwrite all flags, whereas inc and dec do not,
therefore creating false dependencies on earlier instructions that set the
flags. 2-73
Assembly/Compiler Coding Rule 43. (ML impact, L generality) Avoid
rotate by register or rotate by immediate instructions. If possible,
replace with a rotate by 1 instruction. 2-74
Assembly/Compiler Coding Rule 44. (ML impact, L generality) Use
simple instructions that are less than eight bytes in length. 2-76
Assembly/Compiler Coding Rule 45. (M impact, MH generality)
Avoid using prefixes to change the size of immediate and displacement.
2-76
Assembly/Compiler Coding Rule 46. (M impact, MH generality)
Break dependences on portions of registers between instructions by
operating on 32-bit registers instead of partial registers. For moves, this
can be accomplished with 32-bit moves or by using
movzx. 2-76
Assembly/Compiler Coding Rule 47. (M impact, M generality) Try to
use zero extension or operate on 32-bit operands instead of using moves
with sign extension. 2-77
Assembly/Compiler Coding Rule 48. (ML impact, M generality)
Avoid placing instructions that use 32-bit immediates which cannot be
encoded as a sign-extended 16-bit immediate near each other. Try to
schedule µops that have no immediate immediately before or after µops
with 32-bit immediates. 2-77
Assembly/Compiler Coding Rule 49. (M impact, ML generality) Use
xor, sub, or pxor to set a register to 0, or to break a false dependence
chain resulting from re-use of registers. In contexts where the condition
codes must be preserved, move
0 into the register instead. This requires
more code space than using xor and sub, but avoids setting the condition
codes. 2-78
Assembly/Compiler Coding Rule 50. (ML impact, M generality) Use
the
test instruction instead of and when the result of the logical and is
not used. This saves uops in execution. Use a
test if a register with itself

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)