Intel ARCHITECTURE IA-32 User Manual

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Figure 6-2 Memory Access Latency and Execution Without Prefetch .............. 6-23
Figure 6-3 Memory Access Latency and Execution With Prefetch ................... 6-23
Figure 6-4 Prefetch and Loop Unrolling ............................................................ 6-29
Figure 6-5 Memory Access Latency and Execution With Prefetch ................... 6-31
Figure 6-6 Cache Blocking – Temporally Adjacent and Non-adjacent
Passes ............................................................................................. 6-35
Figure 6-7 Examples of Prefetch and Strip-mining for Temporally
Adjacent and Non-Adjacent Passes Loops .....................................6-36
Figure 6-8 Single-Pass Vs. Multi-Pass 3D Geometry Engines ......................... 6-42
Figure 7-1 Amdahl’s Law and MP Speed-up ...................................................... 7-3
Figure 7-2 Single-threaded Execution of Producer-consumer
Threading Model................................................................................ 7-9
Figure 7-3 Execution of Producer-consumer Threading Model on
a Multi-core Processor..................................................................... 7-10
Figure 7-4 Interlaced Variation of the Producer Consumer Model....................7-12
Figure 7-5 Batched Approach of Producer Consumer Model ........................... 7-40
Figure 9-1 Performance History and State Transitions ....................................... 9-3
Figure 9-2 Active Time Versus Halted Time of a Processor ............................... 9-4
Figure 9-3 Application of C-states to Idle Time................................................... 9-6
Figure 9-4 Profiles of Coarse Task Scheduling and Power Consumption.........9-12
Figure 9-5 Thread Migration in a Multi-Core Processor .................................... 9-17
Figure 9-6 Progression to Deeper Sleep .......................................................... 9-18
Figure A-1 Sampling Analysis of Hotspots by Location.....................................A-10
Figure A-2 Intel Thread Checker Can Locate Data Race Conditions................A-18
Figure A-3 Intel Thread Profiler Can Show Critical Paths of Threaded
Execution Timelines.........................................................................A-20
Figure B-1 Relationships Between the Cache Hierarchy, IOQ, BSQ
and Front Side Bus ..........................................................................B-10
Figure D-1 Stack Frames Based on Alignment Type .......................................... D-3
Figure E-1 Pentium II, Pentium III and Pentium 4 Processors Memory
Pipeline Sketch ..................................................................................E-4
Figure E-2 Execution Pipeline, No Preloading or Prefetch..................................E-6
Figure E-3 Compute Bound Execution Pipeline ..................................................E-7
Figure E-4 Another Compute Bound Execution Pipeline.....................................E-8
Figure E-5 Memory Throughput Bound Pipeline ...............................................E-10
Figure E-6 Accesses per Iteration, Example 1 ..................................................E-12
Figure E-7 Accesses per Iteration, Example 2 ..................................................E-13

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)