Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
3-30
but is somewhat inefficient as there is the overhead of extra instructions
during computation. Performing the swizzle statically, when the data
structures are being laid out, is best as there is no runtime overhead.
As mentioned earlier, the SoA arrangement allows more efficient use of
the parallelism of the SIMD technologies because the data is ready for
computation in a more optimal vertical manner: multiplying
components
x0,x1,x2,x3 by xF,xF,xF,xF using 4 SIMD execution
slots to produce 4 unique results. In contrast, computing directly on AoS
data can lead to horizontal operations that consume SIMD execution
slots but produce only a single scalar result as shown by the many
“don’t-care” (DC) slots in Example 3-16.
Use of the SoA format for data structures can also lead to more efficient
use of caches and bandwidth. When the elements of the structure are not
accessed with equal frequency, such as when element
x, y, z are
accessed ten times more often than the other entries, then SoA not only
saves memory, but it also prevents fetching unnecessary data items
a, b,
and
c.
Example 3-17 Hybrid SoA Data Structure
NumOfGroups = NumOfVertices/SIMDwidth
typedef struct{
float x[SIMDwidth];
float y[SIMDwidth];
float z[SIMDwidth];
} VerticesCoordList;
typedef struct{
int a[SIMDwidth];
int b[SIMDwidth];
int c[SIMDwidth];
. . .
} VerticesColorList;
VerticesCoordList VerticesCoord[NumOfGroups];
VerticesColorList VerticesColor[NumOfGroups];

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)