Intel ARCHITECTURE IA-32 User Manual

xxiii
Introduction
The IA-32 Intel
®
Architecture Optimization Reference Manual describes
how to optimize software to take advantage of the performance
characteristics of the current generation of IA-32 Intel architecture
family of processors. The optimizations described in this manual apply
to IA-32 processors based on the Intel
®
NetBurst
®
microarchitecture,
the Intel
®
Pentium
®
M processor family and IA-32 processors that
support Hyper-Threading Technology.
The target audience for this manual includes software programmers and
compiler writers. This manual assumes that the reader is familiar with the
basics of the IA-32 architecture and has access to the Intel
®
Architecture
Software Developer’s Manual: Volume 1, Basic Architecture;
Vo lu me 2 A, Instruction Set Reference A-M; Volume 2B, Instruction Set
Reference N-Z, and Volume 3, System Programmer’s Guide.
When developing and optimizing software applications to achieve a
high level of performance when running on IA-32 processors, a detailed
understanding of IA-32 family of processors is often required. In many
cases, knowledge of IA-32 microarchitectures is required.
This manual provides an overview of the Intel NetBurst
microarchitecture and the Intel Pentium M processor microarchitecture.
It contains design guidelines for high-performance software applications,
coding rules, and techniques for many aspects of code-tuning. These
rules are useful to programmers and compiler developers.
The design guidelines that are discussed in this manual for developing
high-performance software apply to current as well as to future IA-32
processors. The coding rules and code optimization techniques listed

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)