Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
4-22
pxor MM0, MM0
pcmpeq MM1, MM1
psubb MM0, MM1 [psubw MM0, MM1] (psubd MM0, MM1)
; three instructions above generate
; the constant 1 in every
; packed-byte [or packed-word]
; (or packed-dword) field
pcmpeq MM1, MM1
psrlw MM1, 16-n(psrld MM1, 32-n)
; two instructions above generate
; the signed constant 2
n
–1 in every
; packed-word (or packed-dword) field
pcmpeq MM1, MM1
psllw MM1, n (pslld MM1, n)
; two instructions above generate
; the signed constant -2n in every
; packed-word (or packed-dword) field
NOTE. Because the SIMD integer instruction sets do
not support shift instructions for bytes,
2
n
–1 and -2
n
are relevant only for packed words and packed
doublewords.
Example 4-15 Generating Constants (continued)

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)