Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
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Notational Conventions
This manual uses the following conventions:
This type style Indicates an element of syntax, a reserved
word, a keyword, a filename, instruction,
computer output, or part of a program
example. The text appears in lowercase
unless uppercase is significant.
THIS TYPE STYLE Indicates a value, for example, TRUE, CONST1,
or a variable, for example,
A, B, or register
names
MMO through MM7.
l indicates lowercase letter L in examples. 1
is the number 1 in examples.
O is the
uppercase O in examples.
0 is the number 0 in
examples.
This type style Indicates a placeholder for an identifier, an
expression, a string, a symbol, or a value.
Substitute one of these items for the
placeholder.
... (ellipses) Indicate that a few lines of the code are
omitted.
This type style
Indicates a hypertext link.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)