Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
5-28
When targeting complex arithmetics on Intel Core Solo and Intel Core
Duo processors, using single-precision SSE3 instructions can deliver
higher performance than alternatives. On the other hand, tasks requiring
double-precision complex arithmetics may perform better using scalar
SSE2 instructions on Intel Core Solo and Intel Core Duo processors.
This is because scalar SSE2 instructions can be dispatched through two
ports and executed using two separate floating-point units.
Packed horizontal SSE3 instructions (haddps and hsubps) can simplify
the code sequence for some tasks. However, these instruction consist of
more than five micro-ops on Intel Core Solo and Intel Core Duo
processors. Care must be taken to ensure the latency and decoding
penalty of the horizontal instruction does not offset any algorithmic
benefits.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)