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Intel ARCHITECTURE IA-32 User Manual

Intel ARCHITECTURE IA-32
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Multi-Core and Hyper-Threading Technology 7
7-27
If an application thread must remain idle for a long time, the application
should use a thread blocking API or other method to release the idle
processor. The techniques discussed here apply to traditional MP
system, but they have an even higher impact on IA-32 processors that
support Hyper-Threading Technology.
Typically, an operating system provides timing services, for example
Sleep(dwMilliseconds)
6
; such variables can be used to prevent frequent
checking of a synchronization variable.
Another technique to synchronize between worker threads and a control
loop is to use a thread-blocking API provided by the OS. Using a
thread-blocking API allows the control thread to use less processor
cycles for spinning and waiting. This gives the OS more time quanta to
schedule the worker threads on available processors. Furthermore, using
a thread-blocking API also benefits from the system idle loop
optimization that OS implements using the HLT instruction.
User/Source Coding Rule 23. (H impact, M generality) Use a
thread-blocking API in a long idle loop to free up the processor.
Using a spin-wait loop in a traditional MP system may be less of an
issue when the number of runnable threads is less than the number of
processors in the system. If the number of threads in an application is
expected to be greater than the number of processors (either one
processor or multiple processors), use a thread-blocking API to free up
processor resources. A multithreaded application adopting one control
thread to synchronize multiple worker threads may consider limiting
worker threads to the number of processors in a system and use
thread-blocking APIs in the control thread.
6. The Sleep() API is not thread-blocking, because it does not guarantee the processor will be
released.
Example 7-5
(a) shows an example of using Sleep(0), which does not always realize the
processor to another thread.

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Intel ARCHITECTURE IA-32 Specifications

General IconGeneral
Instruction Setx86
Instruction Set TypeCISC
Memory SegmentationSupported
Operating ModesReal mode, Protected mode, Virtual 8086 mode
Max Physical Address Size36 bits (with PAE)
Max Virtual Address Size32 bits
ArchitectureIA-32 (Intel Architecture 32-bit)
Addressable Memory4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers8 x 80-bit
MMX Registers8 x 64-bit
SSE Registers8 x 128-bit
RegistersGeneral-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point UnitYes (x87)

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