Intel ARCHITECTURE IA-32 User Manual

IA-32 Intel® Architecture Optimization
7-62
Write-combining buffers are another example of execution resources
shared between two logical processors. With two threads running
simultaneously on a processor supporting Hyper-Threading Technology,
the
writes of both threads count toward the limit of four
write-combining buffers. For example: if an inner loop that writes to
three separate areas of memory per iteration is run by two threads
simultaneously, the total number of cache lines written could be six.
This being true, the code loses the benefits of write-combining.
Loop-fission applied to this situation creates two loops, neither of which
is allowed to write to more than two cache lines per iteration.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)