Intel ARCHITECTURE IA-32 User Manual

Power Optimization for Mobile Usages 9
9-19
imbalance can be accomplished using performance monitoring
events. Intel Core Duo processor provides an event for this
purpose. The event (Serial_Execution_Cycle) increments under
the following conditions:
— The core is actively executing code in C0 state,
— The second core in the physical processor is in an idle state
(C1-C4).
This event enables software developers to find code that is
executing serially, by comparing Serial_Execution_Cycle and
Unhalted_Ref_Cycles. Changing sections of serialized code to
execute into two parallel threads enables coordinated thread
synchronization to achieve better power savings.
Although Serial_Execution_Cycle is available only on Intel
Core Duo processors, application thread with load-imbalance
situations usually remains the same for symmetric application
threads and on symmetrically configured multi-core processors,
irrespective of differences in their underlying microarchitecture.
For this reason, the technique to identify load-imbalance
situations can be applied to multi-threaded applications in
general, and not specific to Intel Core Duo processors.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)