Intel ARCHITECTURE IA-32 User Manual

Using Performance Monitoring Events B
B-9
There is a simplified block diagram below of the sub-systems connected
to the IOQ unit in the front side bus sub-system and the BSQ unit that
interface to the IOQ. A two-way SMP configuration is illustrated.
1st-level cache misses and writebacks (also called core references)
result in references to the 2nd-level cache. The Bus Sequence Queue
(BSQ) holds requests from the processor core or prefetcher that are to be
serviced on the front side bus (FSB), or in the local XAPIC. If a
3rd-level cache is present on-die, the BSQ also holds writeback requests
(dirty, evicted data) from the 2nd-level cache. The FSB's IOQ holds
requests that have gone out onto the front side bus.

Intel ARCHITECTURE IA-32 Specifications

General

Instruction Set	x86
Instruction Set Type	CISC
Memory Segmentation	Supported
Operating Modes	Real mode, Protected mode, Virtual 8086 mode
Max Physical Address Size	36 bits (with PAE)
Max Virtual Address Size	32 bits
Architecture	IA-32 (Intel Architecture 32-bit)
Addressable Memory	4 GB (with Physical Address Extension up to 64 GB)
Floating Point Registers	8 x 80-bit
MMX Registers	8 x 64-bit
SSE Registers	8 x 128-bit
Registers	General-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP), Segment registers (CS, DS, SS, ES, FS, GS), Instruction pointer (EIP), Flags register (EFLAGS)
Floating Point Unit	Yes (x87)